For the Digital Decimation Filter of DC, a cascaded structure is proposed.
对于ADC中 的数字滤波器部分, 本论文提出了降采样的一种多级级联实现结构.
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Then by changing the decimation ratio of the SINC filter, frequency selecting is realized.
在某一固定输出频率下设计一组带通滤波器, 然后通过改变SINC滤波器 信号抽取比率实现数字选频.
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Design multi - stage decimation system on the basis of Halfband filters and CIC filters.
在半波带滤波器和CIC滤波器的基础上设计了 多级 抽取系统.
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The last 4 times decimation was achieved by two half band filters and a droop FIR.
剩余4倍抽取采用两级半带滤波器和升幅FIR实现.
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A multi - stage decimation filter was designed on the theory of multi - rate digital signal processing.
根据多抽样率数字信号理论,采用 多级 抽取滤波器的设计方法,为陀螺设计输出滤波器.
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